Embodiments relate to a semiconductor package and, more particularly, to a package-on-package type semiconductor package including a wafer level package as a bottom package.
Semiconductor packages have evolved in various directions aiming for compactness, lightness and cost reduction. Moreover, types of packages are also diversified with variety of applications. A ball grid array (BGA) package may be formed by mounting a semiconductor chip on an integrated circuit board, molding the semiconductor chip, and attaching solder balls under the integrated circuit board. The molding structure and the integrated circuit board are necessary to fabricate the BGA package and as a result, there are limits to reduce the thickness of the semiconductor package.
Wafer level packages (WLP) are designed to solve demerits of the BGA package. In the wafer level package process, a redistribution pattern is formed on a bottom side of a semiconductor chip without the molding step and then solder balls are attached to the redistribution pattern. Because the process for the wafer level package does not require a molding structure and an integrated circuit board, it is possible to reduce the thickness of a wafer level package. However, the wafer level package has disadvantages in adhesion of solder balls, handling, and test due to its small size.
Fan-out wafer level packages have been developed to solve these disadvantages. In processes for the fan-out wafer level packages, a molding layer is provided around the semiconductor chip and the redistribution pattern is formed on a bottom side of the molding layer to attach solder balls thereto.